Generally, in the process of making a semiconductor device, an Electrically Erasable Read Only Memory (EEPROM) cell which has both functions of an electrical programming and an electrical erasure can have a stack-gate structure (FIG. 1) and a split-gate structure (FIG. 2).
Referring to FIG. 1, in a conventional flash EEPROM cell having a stack-gate structure, a tunnel oxide film 5, a floating gate 6, an interpoly oxide film 11 and a control gate 12 are sequentially stacked on a selected portion of a silicon substrate 1, and source and drain regions 7 and 8 are formed in the silicon substrate 1 by means of a conventional ion implantation method.
With reference to FIG. 2, in a conventional flash EEPROM cell having the split-gate structure, a tunnel oxide film 5 and a floating gate 6 are sequentially formed on a selected portion of a silicon substrate 1, an interpoly oxide film 11 is then formed on the upper portion of the floating gate 6 and a selected portion of the silicon substrate 1 left to the floating gate 6. A control gate 12 is formed on the interpoly oxide film 11, a source region 7 is formed in the silicon substrate 1 left to the floating gate 6 and a drain region 8 is then formed in the silicon substrate 1 right to the control gate 12. The silicon substrate 1 below the control gate 12 and between the floating gate 6 and the drain region 8 becomes a select channel region 9.
The stack-gate structure has an advantage in that a higher integration density in the device is made possible because it can form a unit cell at a limited area compared to the spilt-gate structure, but it has a disadvantage of an over-erasure in the erasure operation. Whereas, the split-gate structure can solve the problems of the stack-gate structure, but it has difficulties in accomplishing a higher integration density due to the increased area at a unit cell and in controlling the length of select channel to be constant.